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Searched refs:mmRLC_PG_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c3004 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_up()
3009 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_up()
3018 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_down()
3023 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_down()
3032 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_cp_power_gating()
3037 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_cp_power_gating()
3045 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_cg_power_gating()
3050 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_cg_power_gating()
3058 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_pipeline_powergating()
3063 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_pipeline_powergating()
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H A Dgfx_v10_0.c5500 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); in gfx_v10_0_rlc_smu_handshake_cntl()
5514 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); in gfx_v10_0_rlc_smu_handshake_cntl()
5598 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); in gfx_v10_0_rlc_resume()
8376 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); in gfx_v10_cntl_power_gating()
8383 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); in gfx_v10_cntl_power_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h1275 #define mmRLC_PG_CNTL 0x3103 macro
H A Dgfx_7_2_d.h1288 #define mmRLC_PG_CNTL 0x3103 macro
H A Dgfx_8_1_d.h1388 #define mmRLC_PG_CNTL 0xec43 macro
H A Dgfx_8_0_d.h1386 #define mmRLC_PG_CNTL 0xec43 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6037 #define mmRLC_PG_CNTL … macro
H A Dgc_9_1_offset.h6259 #define mmRLC_PG_CNTL … macro
H A Dgc_9_2_1_offset.h6235 #define mmRLC_PG_CNTL … macro
H A Dgc_10_1_0_offset.h9385 #define mmRLC_PG_CNTL … macro