Searched refs:mmRLC_CNTL (Results 1 – 12 of 12) sorted by relevance
| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | polaris10_pwrvirus.h | 49 { 0x00000000, mmRLC_CNTL },
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 1240 #define mmRLC_CNTL 0x30c0 macro
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| H A D | gfx_7_2_d.h | 1253 #define mmRLC_CNTL 0x30c0 macro
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| H A D | gfx_8_1_d.h | 1345 #define mmRLC_CNTL 0xec00 macro
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| H A D | gfx_8_0_d.h | 1342 #define mmRLC_CNTL 0xec00 macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v8_0.c | 5438 rlc_setting = RREG32(mmRLC_CNTL); in gfx_v8_0_is_rlc_enabled()
5449 data = RREG32(mmRLC_CNTL); in gfx_v8_0_set_safe_mode()
5477 data = RREG32(mmRLC_CNTL); in gfx_v8_0_unset_safe_mode()
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| H A D | gfx_v10_0.c | 5481 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_stop()
5484 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); in gfx_v10_0_rlc_stop()
5883 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_backdoor_autoload_enable()
7875 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_is_rlc_enabled()
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| H A D | gfx_v9_0.c | 4942 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v9_0_is_rlc_enabled()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 5963 #define mmRLC_CNTL … macro
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| H A D | gc_9_1_offset.h | 6185 #define mmRLC_CNTL … macro
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| H A D | gc_9_2_1_offset.h | 6149 #define mmRLC_CNTL … macro
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| H A D | gc_10_1_0_offset.h | 9293 #define mmRLC_CNTL … macro
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