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Searched refs:mmRLC_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpolaris10_pwrvirus.h49 { 0x00000000, mmRLC_CNTL },
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2507 tmp = RREG32(mmRLC_CNTL); in gfx_v6_0_update_rlc()
2509 WREG32(mmRLC_CNTL, rlc); in gfx_v6_0_update_rlc()
2516 orig = data = RREG32(mmRLC_CNTL); in gfx_v6_0_halt_rlc()
2520 WREG32(mmRLC_CNTL, data); in gfx_v6_0_halt_rlc()
2530 WREG32(mmRLC_CNTL, 0); in gfx_v6_0_rlc_stop()
2538 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v6_0_rlc_start()
H A Dgfx_v9_0.c4892 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v9_0_is_rlc_enabled()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h1240 #define mmRLC_CNTL 0x30c0 macro
H A Dgfx_7_2_d.h1253 #define mmRLC_CNTL 0x30c0 macro
H A Dgfx_8_1_d.h1345 #define mmRLC_CNTL 0xec00 macro
H A Dgfx_8_0_d.h1342 #define mmRLC_CNTL 0xec00 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h5963 #define mmRLC_CNTL macro
H A Dgc_9_1_offset.h6185 #define mmRLC_CNTL macro
H A Dgc_9_2_1_offset.h6149 #define mmRLC_CNTL macro
H A Dgc_10_1_0_offset.h9293 #define mmRLC_CNTL macro