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Searched refs:mmRLC_CGCG_CGLS_CTRL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c83 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
214 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
244 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
H A Dgfx_v9_0.c3207 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); in gfx_v9_0_rlc_resume()
5109 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v9_0_update_coarse_grain_clock_gating()
5121 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
5130 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
5135 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v9_0_update_gfx_clock_gating()
5326 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); in gfx_v9_0_get_clockgating_state()
H A Dgfx_v6_0.c2617 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v6_0_enable_cgcg()
2648 WREG32(mmRLC_CGCG_CGLS_CTRL, data); in gfx_v6_0_enable_cgcg()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h1281 #define mmRLC_CGCG_CGLS_CTRL 0x3109 macro
H A Dgfx_7_2_d.h1294 #define mmRLC_CGCG_CGLS_CTRL 0x3109 macro
H A Dgfx_8_1_d.h1394 #define mmRLC_CGCG_CGLS_CTRL 0xec49 macro
H A Dgfx_8_0_d.h1392 #define mmRLC_CGCG_CGLS_CTRL 0xec49 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6045 #define mmRLC_CGCG_CGLS_CTRL … macro
H A Dgc_9_1_offset.h6267 #define mmRLC_CGCG_CGLS_CTRL … macro
H A Dgc_9_2_1_offset.h6243 #define mmRLC_CGCG_CGLS_CTRL … macro
H A Dgc_10_1_0_offset.h9393 #define mmRLC_CGCG_CGLS_CTRL … macro