| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mxgpu_vi.c | 83 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
214 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
244 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
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| H A D | gfx_v8_0.c | 206 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
304 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
318 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
349 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
381 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
423 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
467 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
481 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
568 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
578 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
[all …]
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| H A D | gfx_v7_0.c | 3426 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; in gfx_v7_0_rlc_resume()
3427 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); in gfx_v7_0_rlc_resume()
3485 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v7_0_enable_cgcg()
3506 WREG32(mmRLC_CGCG_CGLS_CTRL, data); in gfx_v7_0_enable_cgcg()
3518 WREG32(mmRLC_CGCG_CGLS_CTRL, data); in gfx_v7_0_enable_cgcg()
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| H A D | gfx_v9_0.c | 3165 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); in gfx_v9_0_rlc_resume()
5104 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v9_0_update_coarse_grain_clock_gating()
5116 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
5125 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v9_0_update_coarse_grain_clock_gating()
5130 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
5320 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); in gfx_v9_0_get_clockgating_state()
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| H A D | gfx_v10_0.c | 5453 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); in gfx_v10_0_rlc_resume()
7999 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v10_0_update_coarse_grain_clock_gating()
8011 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
8020 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v10_0_update_coarse_grain_clock_gating()
8031 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
8431 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); in gfx_v10_0_get_clockgating_state()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_6_0_d.h | 1133 #define mmRLC_CGCG_CGLS_CTRL 0x3101 macro
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| H A D | gfx_7_0_d.h | 1281 #define mmRLC_CGCG_CGLS_CTRL 0x3109 macro
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| H A D | gfx_7_2_d.h | 1294 #define mmRLC_CGCG_CGLS_CTRL 0x3109 macro
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| H A D | gfx_8_1_d.h | 1394 #define mmRLC_CGCG_CGLS_CTRL 0xec49 macro
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| H A D | gfx_8_0_d.h | 1392 #define mmRLC_CGCG_CGLS_CTRL 0xec49 macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 6045 #define mmRLC_CGCG_CGLS_CTRL … macro
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| H A D | gc_9_1_offset.h | 6267 #define mmRLC_CGCG_CGLS_CTRL … macro
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| H A D | gc_9_2_1_offset.h | 6243 #define mmRLC_CGCG_CGLS_CTRL … macro
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| H A D | gc_10_1_0_offset.h | 9393 #define mmRLC_CGCG_CGLS_CTRL … macro
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| H A D | gc_10_3_0_offset.h | 9215 #define mmRLC_CGCG_CGLS_CTRL … macro
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