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Searched refs:mmOTG2_OTG_COUNT_CONTROL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_offset.h6989 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_1_0_offset.h6784 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h8434 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h8338 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h9465 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h9196 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX … macro