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Searched refs:mmMPCC3_MPCC_CONTROL_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h3680 #define mmMPCC3_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h10347 #define mmMPCC3_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_1_0_offset.h5464 #define mmMPCC3_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h5707 #define mmMPCC3_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h12681 #define mmMPCC3_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h6645 #define mmMPCC3_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h13992 #define mmMPCC3_MPCC_CONTROL_BASE_IDX … macro