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Searched refs:mmMP0_SMN_C2PMSG_101 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dpsp_v11_0_8.c39 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_8_ring_stop()
45 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_8_ring_stop()
85 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_8_ring_create()
93 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_8_ring_create()
169 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_8_ring_set_wptr()
H A Dpsp_v11_0.c292 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_ring_stop()
304 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_ring_stop()
338 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_ring_create()
346 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_ring_create()
603 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); in psp_v11_0_ring_set_wptr()
/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_12_0_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 … macro
H A Dmp_10_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 … macro
H A Dmp_9_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 0x00a5 macro
H A Dmp_11_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 … macro
H A Dmp_11_0_8_offset.h166 #define mmMP0_SMN_C2PMSG_101 … macro
H A Dmp_11_5_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 … macro