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Searched refs:mmMMSCH_VF_MAILBOX_RESP (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmsch_v2_0.h67 #define mmMMSCH_VF_MAILBOX_RESP … macro
H A Dvcn_v2_0.c1859 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v2_0_start_mmsch()
1876 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_0_start_mmsch()
1880 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_0_start_mmsch()
H A Dvcn_v2_5.c1230 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v2_5_mmsch_start()
1238 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
1242 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
H A Dvcn_v3_0.c1505 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v3_0_start_sriov()
1517 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v3_0_start_sriov()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_offset.h37 #define mmMMSCH_VF_MAILBOX_RESP … macro
H A Dvcn_3_0_0_offset.h65 #define mmMMSCH_VF_MAILBOX_RESP … macro