Home
last modified time | relevance | path

Searched refs:mmMC_SEQ_SUP_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v8_0.c309 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
313 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
314 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_tonga_mc_load_microcode()
326 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
327 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_tonga_mc_load_microcode()
328 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v8_0_tonga_mc_load_microcode()
388 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
389 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_polaris_mc_load_microcode()
396 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
397 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_polaris_mc_load_microcode()
[all …]
H A Dgmc_v6_0.c168 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; in gmc_v6_0_mc_load_microcode()
173 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
174 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v6_0_mc_load_microcode()
186 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
187 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v6_0_mc_load_microcode()
188 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v6_0_mc_load_microcode()
H A Dgmc_v7_0.c199 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
203 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
204 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v7_0_mc_load_microcode()
216 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
217 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v7_0_mc_load_microcode()
218 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v7_0_mc_load_microcode()
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_d.h949 #define mmMC_SEQ_SUP_CNTL 0x0A32 macro
H A Dgmc_7_1_d.h784 #define mmMC_SEQ_SUP_CNTL 0xa32 macro
H A Dgmc_8_1_d.h888 #define mmMC_SEQ_SUP_CNTL 0xa32 macro