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Searched refs:mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h1465 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h1021 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h1059 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h301 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX … macro