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Searched refs:mmLB_INTERRUPT_MASK (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c2959 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vblank_interrupt_state()
2961 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vblank_interrupt_state()
2964 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vblank_interrupt_state()
2966 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vblank_interrupt_state()
3010 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vline_interrupt_state()
3012 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vline_interrupt_state()
3015 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vline_interrupt_state()
3017 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vline_interrupt_state()
H A Ddce_v10_0.c3025 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vblank_interrupt_state()
3028 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vblank_interrupt_state()
3031 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vblank_interrupt_state()
3034 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vblank_interrupt_state()
3054 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vline_interrupt_state()
3057 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vline_interrupt_state()
3060 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vline_interrupt_state()
3063 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vline_interrupt_state()
H A Ddce_v11_0.c3156 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vblank_interrupt_state()
3159 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v11_0_set_crtc_vblank_interrupt_state()
3162 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vblank_interrupt_state()
3165 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v11_0_set_crtc_vblank_interrupt_state()
3185 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vline_interrupt_state()
3188 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v11_0_set_crtc_vline_interrupt_state()
3191 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vline_interrupt_state()
3194 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v11_0_set_crtc_vline_interrupt_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_d.h4593 #define mmLB_INTERRUPT_MASK 0x1ac8 macro
H A Ddce_10_0_d.h5274 #define mmLB_INTERRUPT_MASK 0x1ac8 macro
H A Ddce_11_0_d.h5332 #define mmLB_INTERRUPT_MASK 0x1ac8 macro
H A Ddce_11_2_d.h6589 #define mmLB_INTERRUPT_MASK 0x1ac8 macro