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Searched refs:mmIH_RB_WPTR (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Diceland_ih.c90 WREG32(mmIH_RB_WPTR, 0); in iceland_ih_disable_interrupts()
145 WREG32(mmIH_RB_WPTR, 0); in iceland_ih_irq_init()
201 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
H A Dcz_ih.c90 WREG32(mmIH_RB_WPTR, 0); in cz_ih_disable_interrupts()
145 WREG32(mmIH_RB_WPTR, 0); in cz_ih_irq_init()
201 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
H A Dtonga_ih.c86 WREG32(mmIH_RB_WPTR, 0); in tonga_ih_disable_interrupts()
143 WREG32(mmIH_RB_WPTR, 0); in tonga_ih_irq_init()
203 wptr = RREG32(mmIH_RB_WPTR); in tonga_ih_get_wptr()
H A Dcik_ih.c90 WREG32(mmIH_RB_WPTR, 0); in cik_ih_disable_interrupts()
143 WREG32(mmIH_RB_WPTR, 0); in cik_ih_irq_init()
H A Dvega10_ih.c56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega10_ih_init_register_offset()
H A Dnavi10_ih.c58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in navi10_ih_init_register_offset()
H A Dvega20_ih.c64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega20_ih_init_register_offset()
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_1_0_d.h233 #define mmIH_RB_WPTR 0x0F83 macro
H A Dosssys_4_0_1_offset.h128 #define mmIH_RB_WPTR … macro
H A Dosssys_4_0_offset.h128 #define mmIH_RB_WPTR … macro
H A Dosssys_4_2_0_offset.h130 #define mmIH_RB_WPTR … macro
H A Dosssys_5_0_0_offset.h128 #define mmIH_RB_WPTR … macro
H A Doss_2_4_d.h46 #define mmIH_RB_WPTR 0xe33 macro
H A Doss_3_0_1_d.h46 #define mmIH_RB_WPTR 0xe33 macro
H A Doss_2_0_d.h46 #define mmIH_RB_WPTR 0xf83 macro
H A Doss_3_0_d.h46 #define mmIH_RB_WPTR 0xe33 macro