Searched refs:mmGRPH_FLIP_CONTROL (Results 1 – 9 of 9) sorted by relevance
242 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()245 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_page_flip()2019 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()2022 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
266 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()269 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_page_flip()2069 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()2072 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
192 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? in dce_v8_0_page_flip()1952 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_do_set_base()
201 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? in dce_v6_0_page_flip()1983 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
3830 #define mmGRPH_FLIP_CONTROL 0x1A12 macro
1654 #define mmGRPH_FLIP_CONTROL 0x1a12 macro
2503 #define mmGRPH_FLIP_CONTROL 0x1a12 macro
2397 #define mmGRPH_FLIP_CONTROL 0x1a12 macro
3628 #define mmGRPH_FLIP_CONTROL 0x1a12 macro