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Searched refs:mmGRBM_SOFT_RESET (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h40 #define mmGRBM_SOFT_RESET … macro
H A Dgc_9_0_offset.h47 #define mmGRBM_SOFT_RESET … macro
H A Dgc_9_1_offset.h47 #define mmGRBM_SOFT_RESET … macro
H A Dgc_9_2_1_offset.h47 #define mmGRBM_SOFT_RESET … macro
H A Dgc_10_1_0_offset.h2053 #define mmGRBM_SOFT_RESET … macro
H A Dgc_10_3_0_offset.h2134 #define mmGRBM_SOFT_RESET … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_2.c752 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in sdma_v5_2_start()
755 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in sdma_v5_2_start()
756 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in sdma_v5_2_start()
761 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in sdma_v5_2_start()
762 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in sdma_v5_2_start()
H A Dgfx_v7_0.c3388 u32 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_rlc_reset()
3391 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v7_0_rlc_reset()
3394 WREG32(mmGRBM_SOFT_RESET, tmp);
4590 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4593 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v7_0_soft_reset()
4594 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4599 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v7_0_soft_reset()
4600 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
H A Dgfx_v8_0.c5049 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v8_0_soft_reset()
5052 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v8_0_soft_reset()
5053 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v8_0_soft_reset()
5058 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v8_0_soft_reset()
5059 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v8_0_soft_reset()
H A Dgfx_v9_0.c4132 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v9_0_kiq_read_clock()
4135 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v9_0_kiq_read_clock()
4136 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v9_0_kiq_read_clock()
4141 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v9_0_kiq_read_clock()
4142 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v9_0_kiq_read_clock()
H A Dgfx_v10_0.c7561 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v10_0_get_gpu_clock_counter()
7564 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v10_0_get_gpu_clock_counter()
7565 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v10_0_get_gpu_clock_counter()
7570 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v10_0_get_gpu_clock_counter()
7571 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v10_0_get_gpu_clock_counter()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h776 #define mmGRBM_SOFT_RESET 0x2008 macro
H A Dgfx_7_0_d.h780 #define mmGRBM_SOFT_RESET 0x2008 macro
H A Dgfx_7_2_d.h793 #define mmGRBM_SOFT_RESET 0x2008 macro
H A Dgfx_8_1_d.h867 #define mmGRBM_SOFT_RESET 0x2008 macro
H A Dgfx_8_0_d.h868 #define mmGRBM_SOFT_RESET 0x2008 macro
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c215 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); in fiji_start_avfs_btc()
217 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); in fiji_start_avfs_btc()
H A Dpolaris10_smumgr.c113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); in polaris10_perform_btc()
114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); in polaris10_perform_btc()