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Searched refs:mmGDS_VMID0_BASE (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h2217 #define mmGDS_VMID0_BASE 0x3300 macro
H A Dgfx_7_2_d.h2239 #define mmGDS_VMID0_BASE 0x3300 macro
H A Dgfx_8_1_d.h2416 #define mmGDS_VMID0_BASE 0x3300 macro
H A Dgfx_8_0_d.h2437 #define mmGDS_VMID0_BASE 0x3300 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c2564 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); in gfx_v9_0_init_compute_vmid()
2582 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v9_0_init_gds_vmid()
4274 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, in gfx_v9_0_ring_emit_gds_switch()
4545 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); in gfx_v9_0_do_edc_gds_workarounds()
H A Dgfx_v10_0.c5071 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); in gfx_v10_0_init_compute_vmid()
5092 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v10_0_init_gds_vmid()
7662 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, in gfx_v10_0_ring_emit_gds_switch()
H A Dgfx_v7_0.c94 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
H A Dgfx_v8_0.c179 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h3043 #define mmGDS_VMID0_BASE … macro
H A Dgc_9_1_offset.h3273 #define mmGDS_VMID0_BASE … macro
H A Dgc_9_2_1_offset.h3223 #define mmGDS_VMID0_BASE … macro
H A Dgc_10_1_0_offset.h5543 #define mmGDS_VMID0_BASE … macro
H A Dgc_10_3_0_offset.h5168 #define mmGDS_VMID0_BASE … macro