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Searched refs:mmGCVM_L2_PROTECTION_FAULT_CNTL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v2_1.c428 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_set_fault_enable_default()
458 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v2_1_set_fault_enable_default()
487 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_init()
558 adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_utcl2_harvest()
593 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_save_regs()
H A Dgfxhub_v2_0.c397 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_0_set_fault_enable_default()
427 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v2_0_set_fault_enable_default()
456 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_0_init()
H A Dgfx_v10_0.c338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h3213 #define mmGCVM_L2_PROTECTION_FAULT_CNTL … macro
H A Dgc_10_3_0_offset.h3116 #define mmGCVM_L2_PROTECTION_FAULT_CNTL … macro