Searched refs:mmGB_TILE_MODE0 (Results 1 – 15 of 15) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | cik.c | 1066 {mmGB_TILE_MODE0},
1160 case mmGB_TILE_MODE0: in cik_get_register_value()
1192 idx = (reg_offset - mmGB_TILE_MODE0); in cik_get_register_value()
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| H A D | vi.c | 690 {mmGB_TILE_MODE0},
783 case mmGB_TILE_MODE0: in vi_get_register_value()
815 idx = (reg_offset - mmGB_TILE_MODE0); in vi_get_register_value()
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| H A D | gfx_v6_0.c | 626 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
832 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
1056 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
1280 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
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| H A D | si.c | 1200 case mmGB_TILE_MODE0: in si_get_register_value()
1232 idx = (reg_offset - mmGB_TILE_MODE0); in si_get_register_value()
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| H A D | gfx_v8_0.c | 2251 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2441 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2630 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2833 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3035 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3206 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3383 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
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| H A D | gfx_v7_0.c | 1177 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()
1360 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()
1530 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_6_0_d.h | 658 #define mmGB_TILE_MODE0 0x2644 macro
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| H A D | gfx_7_0_d.h | 692 #define mmGB_TILE_MODE0 0x2644 macro
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| H A D | gfx_7_2_d.h | 705 #define mmGB_TILE_MODE0 0x2644 macro
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| H A D | gfx_8_1_d.h | 777 #define mmGB_TILE_MODE0 0x2644 macro
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| H A D | gfx_8_0_d.h | 777 #define mmGB_TILE_MODE0 0x2644 macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 947 #define mmGB_TILE_MODE0 … macro
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| H A D | gc_9_1_offset.h | 917 #define mmGB_TILE_MODE0 … macro
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| H A D | gc_9_2_1_offset.h | 883 #define mmGB_TILE_MODE0 … macro
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| H A D | gc_10_1_0_offset.h | 2859 #define mmGB_TILE_MODE0 … macro
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