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Searched refs:mmGB_MACROTILE_MODE0 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c2255 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2445 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2634 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2837 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3039 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3210 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3387 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
H A Dgfx_v7_0.c1180 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()
1363 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()
1533 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h724 #define mmGB_MACROTILE_MODE0 0x2664 macro
H A Dgfx_7_2_d.h737 #define mmGB_MACROTILE_MODE0 0x2664 macro
H A Dgfx_8_1_d.h809 #define mmGB_MACROTILE_MODE0 0x2664 macro
H A Dgfx_8_0_d.h809 #define mmGB_MACROTILE_MODE0 0x2664 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1011 #define mmGB_MACROTILE_MODE0 … macro
H A Dgc_9_1_offset.h981 #define mmGB_MACROTILE_MODE0 … macro
H A Dgc_9_2_1_offset.h947 #define mmGB_MACROTILE_MODE0 … macro
H A Dgc_10_1_0_offset.h2923 #define mmGB_MACROTILE_MODE0 … macro