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Searched refs:mmDP5_DP_VID_TIMING_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h9914 #define mmDP5_DP_VID_TIMING_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h11276 #define mmDP5_DP_VID_TIMING_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h12601 #define mmDP5_DP_VID_TIMING_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h12428 #define mmDP5_DP_VID_TIMING_BASE_IDX … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h11631 #define mmDP5_DP_VID_TIMING_BASE_IDX … macro