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Searched refs:mmDP4_DP_SEC_CNTL1_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h9650 #define mmDP4_DP_SEC_CNTL1_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h11234 #define mmDP4_DP_SEC_CNTL1_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h10986 #define mmDP4_DP_SEC_CNTL1_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h12319 #define mmDP4_DP_SEC_CNTL1_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h12130 #define mmDP4_DP_SEC_CNTL1_BASE_IDX … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h11397 #define mmDP4_DP_SEC_CNTL1_BASE_IDX … macro