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Searched refs:mmDP1_DP_MSE_SAT1 (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3194 #define mmDP1_DP_MSE_SAT1 0x1FE5 macro
H A Ddce_8_0_d.h4125 #define mmDP1_DP_MSE_SAT1 0x1fe5 macro
H A Ddce_10_0_d.h4757 #define mmDP1_DP_MSE_SAT1 0x4bd3 macro
H A Ddce_11_0_d.h4818 #define mmDP1_DP_MSE_SAT1 0x4bd3 macro
H A Ddce_11_2_d.h6050 #define mmDP1_DP_MSE_SAT1 0x4bd3 macro
H A Ddce_12_0_offset.h10572 #define mmDP1_DP_MSE_SAT1 … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h5872 #define mmDP1_DP_MSE_SAT1 … macro
H A Ddcn_3_0_3_offset.h5389 #define mmDP1_DP_MSE_SAT1 … macro
H A Ddcn_3_0_1_offset.h8348 #define mmDP1_DP_MSE_SAT1 … macro
H A Ddcn_1_0_offset.h8747 #define mmDP1_DP_MSE_SAT1 … macro
H A Ddcn_2_1_0_offset.h10271 #define mmDP1_DP_MSE_SAT1 … macro
H A Ddcn_3_0_2_offset.h9983 #define mmDP1_DP_MSE_SAT1 … macro
H A Ddcn_2_0_0_offset.h11362 #define mmDP1_DP_MSE_SAT1 … macro
H A Ddcn_3_0_0_offset.h11127 #define mmDP1_DP_MSE_SAT1 … macro