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Searched refs:mmDP1_DP_DPHY_SCRAM_CNTL (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_d.h3925 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x1fd5 macro
H A Ddce_10_0_d.h4557 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 macro
H A Ddce_11_0_d.h4549 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 macro
H A Ddce_11_2_d.h5781 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 macro
H A Ddce_12_0_offset.h10522 #define mmDP1_DP_DPHY_SCRAM_CNTL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h5826 #define mmDP1_DP_DPHY_SCRAM_CNTL … macro
H A Ddcn_3_0_3_offset.h5343 #define mmDP1_DP_DPHY_SCRAM_CNTL … macro
H A Ddcn_3_0_1_offset.h8302 #define mmDP1_DP_DPHY_SCRAM_CNTL … macro
H A Ddcn_1_0_offset.h8701 #define mmDP1_DP_DPHY_SCRAM_CNTL … macro
H A Ddcn_2_1_0_offset.h10225 #define mmDP1_DP_DPHY_SCRAM_CNTL … macro
H A Ddcn_3_0_2_offset.h9937 #define mmDP1_DP_DPHY_SCRAM_CNTL … macro
H A Ddcn_2_0_0_offset.h11316 #define mmDP1_DP_DPHY_SCRAM_CNTL … macro
H A Ddcn_3_0_0_offset.h11081 #define mmDP1_DP_DPHY_SCRAM_CNTL … macro