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Searched refs:mmDP1_DP_DPHY_PRBS_CNTL (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3177 #define mmDP1_DP_DPHY_PRBS_CNTL 0x1FD4 macro
H A Ddce_8_0_d.h3917 #define mmDP1_DP_DPHY_PRBS_CNTL 0x1fd4 macro
H A Ddce_10_0_d.h4549 #define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 macro
H A Ddce_11_0_d.h4539 #define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 macro
H A Ddce_11_2_d.h5771 #define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 macro
H A Ddce_12_0_offset.h10520 #define mmDP1_DP_DPHY_PRBS_CNTL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h5824 #define mmDP1_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_3_0_3_offset.h5341 #define mmDP1_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_3_0_1_offset.h8300 #define mmDP1_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_1_0_offset.h8699 #define mmDP1_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_2_1_0_offset.h10223 #define mmDP1_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_3_0_2_offset.h9935 #define mmDP1_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_2_0_0_offset.h11314 #define mmDP1_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_3_0_0_offset.h11079 #define mmDP1_DP_DPHY_PRBS_CNTL … macro