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Searched refs:mmDP0_DP_VID_TIMING (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3166 #define mmDP0_DP_VID_TIMING 0x1CC9 macro
H A Ddce_8_0_d.h3812 #define mmDP0_DP_VID_TIMING 0x1cc9 macro
H A Ddce_10_0_d.h4444 #define mmDP0_DP_VID_TIMING 0x4aa8 macro
H A Ddce_11_0_d.h4408 #define mmDP0_DP_VID_TIMING 0x4aa8 macro
H A Ddce_11_2_d.h5640 #define mmDP0_DP_VID_TIMING 0x4aa8 macro
H A Ddce_12_0_offset.h10210 #define mmDP0_DP_VID_TIMING … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5478 #define mmDP0_DP_VID_TIMING … macro
H A Ddcn_3_0_3_offset.h4972 #define mmDP0_DP_VID_TIMING … macro
H A Ddcn_3_0_1_offset.h7934 #define mmDP0_DP_VID_TIMING … macro
H A Ddcn_1_0_offset.h8363 #define mmDP0_DP_VID_TIMING … macro
H A Ddcn_2_1_0_offset.h9867 #define mmDP0_DP_VID_TIMING … macro
H A Ddcn_3_0_2_offset.h9566 #define mmDP0_DP_VID_TIMING … macro
H A Ddcn_2_0_0_offset.h10960 #define mmDP0_DP_VID_TIMING … macro
H A Ddcn_3_0_0_offset.h10710 #define mmDP0_DP_VID_TIMING … macro