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Searched refs:mmDP0_DP_SEC_CNTL1 (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3151 #define mmDP0_DP_SEC_CNTL1 0x1CAB macro
H A Ddce_8_0_d.h4012 #define mmDP0_DP_SEC_CNTL1 0x1cab macro
H A Ddce_10_0_d.h4644 #define mmDP0_DP_SEC_CNTL1 0x4ac4 macro
H A Ddce_11_0_d.h4677 #define mmDP0_DP_SEC_CNTL1 0x4ac4 macro
H A Ddce_11_2_d.h5909 #define mmDP0_DP_SEC_CNTL1 0x4ac4 macro
H A Ddce_12_0_offset.h10260 #define mmDP0_DP_SEC_CNTL1 … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h5524 #define mmDP0_DP_SEC_CNTL1 … macro
H A Ddcn_3_0_3_offset.h5018 #define mmDP0_DP_SEC_CNTL1 … macro
H A Ddcn_3_0_1_offset.h7980 #define mmDP0_DP_SEC_CNTL1 … macro
H A Ddcn_1_0_offset.h8409 #define mmDP0_DP_SEC_CNTL1 … macro
H A Ddcn_2_1_0_offset.h9913 #define mmDP0_DP_SEC_CNTL1 … macro
H A Ddcn_3_0_2_offset.h9612 #define mmDP0_DP_SEC_CNTL1 … macro
H A Ddcn_2_0_0_offset.h11006 #define mmDP0_DP_SEC_CNTL1 … macro
H A Ddcn_3_0_0_offset.h10756 #define mmDP0_DP_SEC_CNTL1 … macro