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Searched refs:mmDP0_DP_DPHY_PRBS_CNTL (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3125 #define mmDP0_DP_DPHY_PRBS_CNTL 0x1CD4 macro
H A Ddce_8_0_d.h3916 #define mmDP0_DP_DPHY_PRBS_CNTL 0x1cd4 macro
H A Ddce_10_0_d.h4548 #define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 macro
H A Ddce_11_0_d.h4538 #define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 macro
H A Ddce_11_2_d.h5770 #define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 macro
H A Ddce_12_0_offset.h10236 #define mmDP0_DP_DPHY_PRBS_CNTL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h5504 #define mmDP0_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_3_0_3_offset.h4998 #define mmDP0_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_3_0_1_offset.h7960 #define mmDP0_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_1_0_offset.h8389 #define mmDP0_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_2_1_0_offset.h9893 #define mmDP0_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_3_0_2_offset.h9592 #define mmDP0_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_2_0_0_offset.h10986 #define mmDP0_DP_DPHY_PRBS_CNTL … macro
H A Ddcn_3_0_0_offset.h10736 #define mmDP0_DP_DPHY_PRBS_CNTL … macro