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Searched refs:mmDIG5_TMDS_DCBALANCER_CONTROL (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h2983 #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4B84 macro
H A Ddce_8_0_d.h3469 #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4b84 macro
H A Ddce_10_0_d.h4248 #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 macro
H A Ddce_11_0_d.h4193 #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 macro
H A Ddce_11_2_d.h5424 #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 macro
H A Ddce_12_0_offset.h11600 #define mmDIG5_TMDS_DCBALANCER_CONTROL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h9881 #define mmDIG5_TMDS_DCBALANCER_CONTROL … macro
H A Ddcn_3_0_2_offset.h11242 #define mmDIG5_TMDS_DCBALANCER_CONTROL … macro
H A Ddcn_2_0_0_offset.h12562 #define mmDIG5_TMDS_DCBALANCER_CONTROL … macro
H A Ddcn_3_0_0_offset.h12394 #define mmDIG5_TMDS_DCBALANCER_CONTROL … macro