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Searched refs:mmDIG3_TMDS_STEREOSYNC_CTL_SEL (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h2815 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457F macro
H A Ddce_8_0_d.h3427 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457f macro
H A Ddce_10_0_d.h4206 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e macro
H A Ddce_11_0_d.h4141 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e macro
H A Ddce_11_2_d.h5372 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e macro
H A Ddce_12_0_offset.h11024 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_offset.h8916 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_1_0_offset.h9253 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_2_1_0_offset.h10809 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_3_0_2_offset.h10554 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_2_0_0_offset.h11898 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_3_0_0_offset.h11698 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL … macro