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Searched refs:mmDIG2_TMDS_STEREOSYNC_CTL_SEL (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h2730 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427F macro
H A Ddce_8_0_d.h3426 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427f macro
H A Ddce_10_0_d.h4205 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e macro
H A Ddce_11_0_d.h4140 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e macro
H A Ddce_11_2_d.h5371 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e macro
H A Ddce_12_0_offset.h10740 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_offset.h8576 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_1_0_offset.h8943 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_2_1_0_offset.h10479 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_3_0_2_offset.h10211 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_2_0_0_offset.h11570 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_3_0_0_offset.h11355 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL … macro