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Searched refs:mmDIG1_DIG_LANE_ENABLE (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h2613 #define mmDIG1_DIG_LANE_ENABLE 0x1F8D macro
H A Ddce_8_0_d.h3497 #define mmDIG1_DIG_LANE_ENABLE 0x1f8d macro
H A Ddce_10_0_d.h4286 #define mmDIG1_DIG_LANE_ENABLE 0x4b79 macro
H A Ddce_11_0_d.h4229 #define mmDIG1_DIG_LANE_ENABLE 0x4b79 macro
H A Ddce_11_2_d.h5460 #define mmDIG1_DIG_LANE_ENABLE 0x4b79 macro
H A Ddce_12_0_offset.h10472 #define mmDIG1_DIG_LANE_ENABLE … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h5772 #define mmDIG1_DIG_LANE_ENABLE … macro
H A Ddcn_3_0_3_offset.h5292 #define mmDIG1_DIG_LANE_ENABLE … macro
H A Ddcn_3_0_1_offset.h8250 #define mmDIG1_DIG_LANE_ENABLE … macro
H A Ddcn_1_0_offset.h8649 #define mmDIG1_DIG_LANE_ENABLE … macro
H A Ddcn_2_1_0_offset.h10167 #define mmDIG1_DIG_LANE_ENABLE … macro
H A Ddcn_3_0_2_offset.h9886 #define mmDIG1_DIG_LANE_ENABLE … macro
H A Ddcn_2_0_0_offset.h11260 #define mmDIG1_DIG_LANE_ENABLE … macro
H A Ddcn_3_0_0_offset.h11030 #define mmDIG1_DIG_LANE_ENABLE … macro