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Searched refs:mmDIG0_TMDS_STEREOSYNC_CTL_SEL (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h2560 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1C7F macro
H A Ddce_8_0_d.h3424 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1c7f macro
H A Ddce_10_0_d.h4203 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e macro
H A Ddce_11_0_d.h4138 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e macro
H A Ddce_11_2_d.h5369 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e macro
H A Ddce_12_0_offset.h10172 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h5434 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_3_0_3_offset.h4931 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_3_0_1_offset.h7896 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_1_0_offset.h8323 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_2_1_0_offset.h9819 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_3_0_2_offset.h9525 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_2_0_0_offset.h10914 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … macro
H A Ddcn_3_0_0_offset.h10669 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … macro