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Searched refs:mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h5447 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h4944 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … macro
H A Ddcn_1_0_offset.h8334 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h9832 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h9538 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h10927 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h10682 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h10183 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … macro