Home
last modified time | relevance | path

Searched refs:mmDC_HPD1_INT_CONTROL (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c260 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v8_0_hpd_set_polarity()
265 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v8_0_hpd_set_polarity()
278 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v8_0_hpd_int_ack()
280 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v8_0_hpd_int_ack()
316 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v8_0_hpd_init()
318 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v8_0_hpd_init()
3019 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); in dce_v8_0_set_hpd_irq_state()
3021 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); in dce_v8_0_set_hpd_irq_state()
3024 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); in dce_v8_0_set_hpd_irq_state()
3026 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); in dce_v8_0_set_hpd_irq_state()
H A Ddce_v6_0.c276 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_set_polarity()
281 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_set_polarity()
294 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_int_ack()
296 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_int_ack()
332 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_init()
334 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_init()
3003 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_set_hpd_irq_state()
3005 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], dc_hpd_int_cntl); in dce_v6_0_set_hpd_irq_state()
3008 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_set_hpd_irq_state()
3010 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], dc_hpd_int_cntl); in dce_v6_0_set_hpd_irq_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h1283 #define mmDC_HPD1_INT_CONTROL 0x1808 macro
H A Ddce_8_0_d.h3513 #define mmDC_HPD1_INT_CONTROL 0x1808 macro