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Searched refs:mmDC_GPU_TIMER_READ_CNTL (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h1278 #define mmDC_GPU_TIMER_READ_CNTL 0x192A macro
H A Ddce_8_0_d.h1298 #define mmDC_GPU_TIMER_READ_CNTL 0x192a macro
H A Ddce_10_0_d.h1585 #define mmDC_GPU_TIMER_READ_CNTL 0x482c macro
H A Ddce_11_0_d.h1410 #define mmDC_GPU_TIMER_READ_CNTL 0x482c macro
H A Ddce_11_2_d.h1490 #define mmDC_GPU_TIMER_READ_CNTL 0x482c macro
H A Ddce_12_0_offset.h1884 #define mmDC_GPU_TIMER_READ_CNTL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h457 #define mmDC_GPU_TIMER_READ_CNTL … macro
H A Ddcn_3_0_1_offset.h656 #define mmDC_GPU_TIMER_READ_CNTL … macro
H A Ddcn_1_0_offset.h1076 #define mmDC_GPU_TIMER_READ_CNTL … macro
H A Ddcn_2_1_0_offset.h712 #define mmDC_GPU_TIMER_READ_CNTL … macro
H A Ddcn_3_0_2_offset.h630 #define mmDC_GPU_TIMER_READ_CNTL … macro
H A Ddcn_2_0_0_offset.h750 #define mmDC_GPU_TIMER_READ_CNTL … macro
H A Ddcn_3_0_0_offset.h648 #define mmDC_GPU_TIMER_READ_CNTL … macro