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Searched refs:mmD1VGA_CONTROL (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v9_0.c1279 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); in gmc_v9_0_get_vbios_fb_size()
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h1041 #define mmD1VGA_CONTROL 0x00CC macro
H A Ddce_8_0_d.h5144 #define mmD1VGA_CONTROL 0xcc macro
H A Ddce_10_0_d.h6027 #define mmD1VGA_CONTROL 0xcc macro
H A Ddce_11_0_d.h6104 #define mmD1VGA_CONTROL 0xcc macro
H A Ddce_11_2_d.h7778 #define mmD1VGA_CONTROL 0xcc macro
H A Ddce_12_0_offset.h574 #define mmD1VGA_CONTROL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h37 #define mmD1VGA_CONTROL … macro
H A Ddcn_3_0_1_offset.h168 #define mmD1VGA_CONTROL … macro
H A Ddcn_1_0_offset.h408 #define mmD1VGA_CONTROL … macro
H A Ddcn_2_1_0_offset.h112 #define mmD1VGA_CONTROL … macro
H A Ddcn_3_0_2_offset.h52 #define mmD1VGA_CONTROL … macro
H A Ddcn_2_0_0_offset.h52 #define mmD1VGA_CONTROL … macro
H A Ddcn_3_0_0_offset.h34 #define mmD1VGA_CONTROL … macro