Searched refs:mmD1VGA_CONTROL (Results 1 – 23 of 23) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dce120/ |
| H A D | dce120_timing_generator.c | 398 offset = mmD2VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
401 offset = mmD3VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
404 offset = mmD4VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
407 offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
410 offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
416 value = dm_read_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset); in dce120_timing_generator_disable_vga()
424 dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value); in dce120_timing_generator_disable_vga()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gmc_v10_0.c | 543 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); in gmc_v10_0_get_vbios_fb_size()
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| H A D | gmc_v6_0.c | 797 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); in gmc_v6_0_get_vbios_fb_size()
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| H A D | gmc_v7_0.c | 968 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); in gmc_v7_0_get_vbios_fb_size()
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| H A D | gmc_v8_0.c | 1076 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); in gmc_v8_0_get_vbios_fb_size()
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| H A D | gmc_v9_0.c | 1338 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); in gmc_v9_0_get_vbios_fb_size()
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| H A D | dce_v8_0.c | 1752 mmD1VGA_CONTROL,
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| H A D | dce_v10_0.c | 1805 mmD1VGA_CONTROL,
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| H A D | dce_v6_0.c | 1849 mmD1VGA_CONTROL,
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_timing_generator.c | 1807 addr = mmD1VGA_CONTROL; in dce110_timing_generator_disable_vga()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/dce/ |
| H A D | dce_6_0_d.h | 1041 #define mmD1VGA_CONTROL 0x00CC macro
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| H A D | dce_8_0_d.h | 5144 #define mmD1VGA_CONTROL 0xcc macro
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| H A D | dce_10_0_d.h | 6027 #define mmD1VGA_CONTROL 0xcc macro
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| H A D | dce_11_0_d.h | 6104 #define mmD1VGA_CONTROL 0xcc macro
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| H A D | dce_11_2_d.h | 7778 #define mmD1VGA_CONTROL 0xcc macro
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| H A D | dce_12_0_offset.h | 574 #define mmD1VGA_CONTROL … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/dcn/ |
| H A D | dcn_3_0_3_offset.h | 37 #define mmD1VGA_CONTROL … macro
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| H A D | dcn_3_0_1_offset.h | 168 #define mmD1VGA_CONTROL … macro
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| H A D | dcn_1_0_offset.h | 408 #define mmD1VGA_CONTROL … macro
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| H A D | dcn_2_1_0_offset.h | 112 #define mmD1VGA_CONTROL … macro
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| H A D | dcn_3_0_2_offset.h | 52 #define mmD1VGA_CONTROL … macro
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| H A D | dcn_2_0_0_offset.h | 52 #define mmD1VGA_CONTROL … macro
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| H A D | dcn_3_0_0_offset.h | 34 #define mmD1VGA_CONTROL … macro
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