Home
last modified time | relevance | path

Searched refs:mmCP_SEM_WAIT_TIMER_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h4726 #define mmCP_SEM_WAIT_TIMER_BASE_IDX … macro
H A Dgc_9_1_offset.h4956 #define mmCP_SEM_WAIT_TIMER_BASE_IDX … macro
H A Dgc_9_2_1_offset.h4912 #define mmCP_SEM_WAIT_TIMER_BASE_IDX … macro
H A Dgc_10_1_0_offset.h7220 #define mmCP_SEM_WAIT_TIMER_BASE_IDX … macro