Home
last modified time | relevance | path

Searched refs:mmCP_RB_WPTR_POLL_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c2964 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); in gfx_v9_0_init_gfx_power_gating()
2967 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); in gfx_v9_0_init_gfx_power_gating()
5116 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_3d_clock_gating()
5120 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_3d_clock_gating()
5166 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_coarse_grain_clock_gating()
5170 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
H A Dgfx_v8_0.c303 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
466 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
567 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
673 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
H A Dgfx_v10_0.c8053 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v10_0_update_3d_clock_gating()
8057 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v10_0_update_3d_clock_gating()
8113 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v10_0_update_coarse_grain_clock_gating()
8117 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h513 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
H A Dgfx_7_2_d.h526 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
H A Dgfx_8_1_d.h579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
H A Dgfx_8_0_d.h579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h217 #define mmCP_RB_WPTR_POLL_CNTL … macro
H A Dgc_9_1_offset.h217 #define mmCP_RB_WPTR_POLL_CNTL … macro
H A Dgc_9_2_1_offset.h211 #define mmCP_RB_WPTR_POLL_CNTL … macro
H A Dgc_10_1_0_offset.h2219 #define mmCP_RB_WPTR_POLL_CNTL … macro