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Searched refs:mmCP_RB2_BASE (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h506 #define mmCP_RB2_BASE 0x3065 macro
H A Dgfx_7_0_d.h200 #define mmCP_RB2_BASE 0x3065 macro
H A Dgfx_7_2_d.h200 #define mmCP_RB2_BASE 0x3065 macro
H A Dgfx_8_1_d.h225 #define mmCP_RB2_BASE 0x3065 macro
H A Dgfx_8_0_d.h224 #define mmCP_RB2_BASE 0x3065 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2192 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); in gfx_v6_0_cp_compute_resume()
H A Dgfx_v9_0.c174 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
H A Dgfx_v10_0.c304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2456 #define mmCP_RB2_BASE … macro
H A Dgc_9_1_offset.h2733 #define mmCP_RB2_BASE … macro
H A Dgc_9_2_1_offset.h2671 #define mmCP_RB2_BASE … macro
H A Dgc_10_1_0_offset.h4799 #define mmCP_RB2_BASE … macro
H A Dgc_10_3_0_offset.h4452 #define mmCP_RB2_BASE … macro