Home
last modified time | relevance | path

Searched refs:mmCP_RB1_WPTR_HI (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2430 #define mmCP_RB1_WPTR_HI … macro
H A Dgc_9_1_offset.h2707 #define mmCP_RB1_WPTR_HI … macro
H A Dgc_9_2_1_offset.h2645 #define mmCP_RB1_WPTR_HI … macro
H A Dgc_10_1_0_offset.h4771 #define mmCP_RB1_WPTR_HI … macro
H A Dgc_10_3_0_offset.h4424 #define mmCP_RB1_WPTR_HI … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c6437 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()