Home
last modified time | relevance | path

Searched refs:mmCP_RB1_WPTR (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h216 #define mmCP_RB1_WPTR 0x3064 macro
H A Dgfx_7_2_d.h216 #define mmCP_RB1_WPTR 0x3064 macro
H A Dgfx_8_1_d.h241 #define mmCP_RB1_WPTR 0x3064 macro
H A Dgfx_8_0_d.h240 #define mmCP_RB1_WPTR 0x3064 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2428 #define mmCP_RB1_WPTR … macro
H A Dgc_9_1_offset.h2705 #define mmCP_RB1_WPTR … macro
H A Dgc_9_2_1_offset.h2643 #define mmCP_RB1_WPTR … macro
H A Dgc_10_1_0_offset.h4769 #define mmCP_RB1_WPTR … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
6578 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
H A Dgfx_v9_0.c173 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),