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Searched refs:mmCP_RB1_RPTR_ADDR_HI (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h504 #define mmCP_RB1_RPTR_ADDR_HI 0x3063 macro
H A Dgfx_7_0_d.h212 #define mmCP_RB1_RPTR_ADDR_HI 0x3063 macro
H A Dgfx_7_2_d.h212 #define mmCP_RB1_RPTR_ADDR_HI 0x3063 macro
H A Dgfx_8_1_d.h237 #define mmCP_RB1_RPTR_ADDR_HI 0x3063 macro
H A Dgfx_8_0_d.h236 #define mmCP_RB1_RPTR_ADDR_HI 0x3063 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2454 #define mmCP_RB1_RPTR_ADDR_HI … macro
H A Dgc_9_1_offset.h2731 #define mmCP_RB1_RPTR_ADDR_HI … macro
H A Dgc_9_2_1_offset.h2669 #define mmCP_RB1_RPTR_ADDR_HI … macro
H A Dgc_10_1_0_offset.h4795 #define mmCP_RB1_RPTR_ADDR_HI … macro
H A Dgc_10_3_0_offset.h4448 #define mmCP_RB1_RPTR_ADDR_HI … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c6441 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v10_0_cp_gfx_resume()