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Searched refs:mmCP_RB1_CNTL (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h501 #define mmCP_RB1_CNTL 0x3061 macro
H A Dgfx_7_0_d.h203 #define mmCP_RB1_CNTL 0x3061 macro
H A Dgfx_7_2_d.h203 #define mmCP_RB1_CNTL 0x3061 macro
H A Dgfx_8_1_d.h228 #define mmCP_RB1_CNTL 0x3061 macro
H A Dgfx_8_0_d.h227 #define mmCP_RB1_CNTL 0x3061 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2161 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
2163 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_compute_resume()
2172 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
H A Dgfx_v10_0.c6410 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); in gfx_v10_0_cp_compute_enable()
6427 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); in gfx_v10_0_cp_compute_enable()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2450 #define mmCP_RB1_CNTL … macro
H A Dgc_9_1_offset.h2727 #define mmCP_RB1_CNTL … macro
H A Dgc_9_2_1_offset.h2665 #define mmCP_RB1_CNTL … macro
H A Dgc_10_1_0_offset.h4791 #define mmCP_RB1_CNTL … macro
H A Dgc_10_3_0_offset.h4444 #define mmCP_RB1_CNTL … macro