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Searched refs:mmCP_RB0_WPTR_HI (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c3347 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v9_0_cp_compute_load_microcode()
5324 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; in gfx_v9_0_ring_emit_ib_gfx()
5340 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v9_0_ring_patch_cntl()
H A Dgfx_v10_0.c6375 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
8449 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; in gfx_v10_0_ring_emit_hdp_flush()
8467 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, in gfx_v10_0_ring_emit_hdp_flush()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2424 #define mmCP_RB0_WPTR_HI … macro
H A Dgc_9_1_offset.h2701 #define mmCP_RB0_WPTR_HI … macro
H A Dgc_9_2_1_offset.h2639 #define mmCP_RB0_WPTR_HI … macro
H A Dgc_10_1_0_offset.h4765 #define mmCP_RB0_WPTR_HI … macro
H A Dgc_10_3_0_offset.h4418 #define mmCP_RB0_WPTR_HI … macro