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Searched refs:mmCP_RB0_RPTR_ADDR (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h497 #define mmCP_RB0_RPTR_ADDR 0x3043 macro
H A Dgfx_7_0_d.h206 #define mmCP_RB0_RPTR_ADDR 0x3043 macro
H A Dgfx_7_2_d.h206 #define mmCP_RB0_RPTR_ADDR 0x3043 macro
H A Dgfx_8_1_d.h231 #define mmCP_RB0_RPTR_ADDR 0x3043 macro
H A Dgfx_8_0_d.h230 #define mmCP_RB0_RPTR_ADDR 0x3043 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2372 #define mmCP_RB0_RPTR_ADDR … macro
H A Dgc_9_1_offset.h2649 #define mmCP_RB0_RPTR_ADDR … macro
H A Dgc_9_2_1_offset.h2587 #define mmCP_RB0_RPTR_ADDR … macro
H A Dgc_10_1_0_offset.h4717 #define mmCP_RB0_RPTR_ADDR … macro
H A Dgc_10_3_0_offset.h4372 #define mmCP_RB0_RPTR_ADDR … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2564 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v7_0_cp_gfx_resume()
H A Dgfx_v8_0.c4265 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v8_0_cp_gfx_resume()
H A Dgfx_v9_0.c3380 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v9_0_cp_gfx_resume()
H A Dgfx_v10_0.c6402 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v10_0_cp_gfx_resume()