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Searched refs:mmCP_RB0_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpolaris10_pwrvirus.h54 { 0x0840800a, mmCP_RB0_CNTL },
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2161 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v6_0_cp_gfx_resume()
2164 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_gfx_resume()
2176 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v6_0_cp_gfx_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h201 #define mmCP_RB0_CNTL 0x3041 macro
H A Dgfx_7_2_d.h201 #define mmCP_RB0_CNTL 0x3041 macro
H A Dgfx_8_1_d.h226 #define mmCP_RB0_CNTL 0x3041 macro
H A Dgfx_8_0_d.h225 #define mmCP_RB0_CNTL 0x3041 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2366 #define mmCP_RB0_CNTL … macro
H A Dgc_9_1_offset.h2643 #define mmCP_RB0_CNTL … macro
H A Dgc_9_2_1_offset.h2581 #define mmCP_RB0_CNTL … macro
H A Dgc_10_1_0_offset.h4711 #define mmCP_RB0_CNTL … macro