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Searched refs:mmCP_RB0_BASE (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h195 #define mmCP_RB0_BASE 0x3040 macro
H A Dgfx_7_2_d.h195 #define mmCP_RB0_BASE 0x3040 macro
H A Dgfx_8_1_d.h220 #define mmCP_RB0_BASE 0x3040 macro
H A Dgfx_8_0_d.h219 #define mmCP_RB0_BASE 0x3040 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2178 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); in gfx_v6_0_cp_gfx_resume()
H A Dgfx_v9_0.c168 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
3433 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); in gfx_v9_0_cp_gfx_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2362 #define mmCP_RB0_BASE … macro
H A Dgc_9_1_offset.h2639 #define mmCP_RB0_BASE … macro
H A Dgc_9_2_1_offset.h2577 #define mmCP_RB0_BASE … macro
H A Dgc_10_1_0_offset.h4707 #define mmCP_RB0_BASE … macro