Searched refs:mmCP_PQ_WPTR_POLL_CNTL1 (Results 1 – 13 of 13) sorted by relevance
| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | polaris10_pwrvirus.h | 1785 { 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1 },
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v10_3.c | 259 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, in hqd_load_v10_3()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 273 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, in kgd_hqd_load()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 285 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1, in kgd_gfx_v9_hqd_load()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 263 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
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| H A D | gfx_7_2_d.h | 265 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
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| H A D | gfx_8_1_d.h | 296 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
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| H A D | gfx_8_0_d.h | 296 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2499 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro
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| H A D | gc_9_1_offset.h | 2773 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro
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| H A D | gc_9_2_1_offset.h | 2709 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro
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| H A D | gc_10_1_0_offset.h | 4839 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro
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| H A D | gc_10_3_0_offset.h | 4498 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro
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