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Searched refs:mmCP_MQD_CONTROL (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v7.c176 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) in kgd_hqd_load()
228 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) in kgd_hqd_dump()
H A Dgfx_v9_0.c3617 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); in gfx_v9_0_mqd_init()
3728 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, in gfx_v9_0_kiq_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h601 #define mmCP_MQD_CONTROL 0x3267 macro
H A Dgfx_7_2_d.h614 #define mmCP_MQD_CONTROL 0x3267 macro
H A Dgfx_8_1_d.h667 #define mmCP_MQD_CONTROL 0x3267 macro
H A Dgfx_8_0_d.h667 #define mmCP_MQD_CONTROL 0x3267 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2891 #define mmCP_MQD_CONTROL … macro
H A Dgc_9_1_offset.h3119 #define mmCP_MQD_CONTROL … macro
H A Dgc_9_2_1_offset.h3075 #define mmCP_MQD_CONTROL … macro
H A Dgc_10_1_0_offset.h5375 #define mmCP_MQD_CONTROL … macro