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Searched refs:mmCP_MQD_BASE_ADDR (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpolaris10_pwrvirus.h1505 { 0x54116f00, mmCP_MQD_BASE_ADDR },
1515 { 0x54117300, mmCP_MQD_BASE_ADDR },
1525 { 0x54117700, mmCP_MQD_BASE_ADDR },
1535 { 0x54117b00, mmCP_MQD_BASE_ADDR },
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v8.c186 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) in kgd_hqd_load()
187 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); in kgd_hqd_load()
201 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); in kgd_hqd_load()
252 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++) in kgd_hqd_dump()
H A Damdgpu_amdkfd_gfx_v7.c176 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) in kgd_hqd_load()
177 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); in kgd_hqd_load()
228 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) in kgd_hqd_dump()
H A Damdgpu_amdkfd_gfx_v10_3.c210 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in hqd_load_v10_3()
347 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in hqd_dump_v10_3()
H A Damdgpu_amdkfd_gfx_v10.c224 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_load()
361 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_dump()
H A Damdgpu_amdkfd_gfx_v9.c238 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_load()
372 for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_dump()
H A Dgfx_v9_0.c3722 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, in gfx_v9_0_kiq_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h567 #define mmCP_MQD_BASE_ADDR 0x3245 macro
H A Dgfx_7_2_d.h580 #define mmCP_MQD_BASE_ADDR 0x3245 macro
H A Dgfx_8_1_d.h630 #define mmCP_MQD_BASE_ADDR 0x3245 macro
H A Dgfx_8_0_d.h630 #define mmCP_MQD_BASE_ADDR 0x3245 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2819 #define mmCP_MQD_BASE_ADDR … macro
H A Dgc_9_1_offset.h3047 #define mmCP_MQD_BASE_ADDR … macro
H A Dgc_9_2_1_offset.h3003 #define mmCP_MQD_BASE_ADDR … macro
H A Dgc_10_1_0_offset.h5303 #define mmCP_MQD_BASE_ADDR … macro