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Searched refs:mmCP_ME_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpolaris10_pwrvirus.h51 { 0x15000000, mmCP_ME_CNTL },
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h505 #define mmCP_ME_CNTL 0x21b6 macro
H A Dgfx_7_2_d.h518 #define mmCP_ME_CNTL 0x21b6 macro
H A Dgfx_8_1_d.h571 #define mmCP_ME_CNTL 0x21b6 macro
H A Dgfx_8_0_d.h571 #define mmCP_ME_CNTL 0x21b6 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2005 WREG32(mmCP_ME_CNTL, 0); in gfx_v6_0_cp_gfx_enable()
2007 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | in gfx_v6_0_cp_gfx_enable()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h197 #define mmCP_ME_CNTL … macro
H A Dgc_9_1_offset.h197 #define mmCP_ME_CNTL … macro
H A Dgc_9_2_1_offset.h191 #define mmCP_ME_CNTL … macro
H A Dgc_10_1_0_offset.h2199 #define mmCP_ME_CNTL … macro