Searched refs:mmCP_ME_CNTL (Results 1 – 12 of 12) sorted by relevance
| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | polaris10_pwrvirus.h | 51 { 0x15000000, mmCP_ME_CNTL },
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 505 #define mmCP_ME_CNTL 0x21b6 macro
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| H A D | gfx_7_2_d.h | 518 #define mmCP_ME_CNTL 0x21b6 macro
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| H A D | gfx_8_1_d.h | 571 #define mmCP_ME_CNTL 0x21b6 macro
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| H A D | gfx_8_0_d.h | 571 #define mmCP_ME_CNTL 0x21b6 macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v8_0.c | 4099 u32 tmp = RREG32(mmCP_ME_CNTL); in gfx_v8_0_cp_gfx_enable()
4110 WREG32(mmCP_ME_CNTL, tmp); in gfx_v8_0_cp_gfx_enable()
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| H A D | gfx_v9_0.c | 3248 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); in gfx_v9_0_cp_gfx_enable()
3262 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v9_0_cp_gfx_enable()
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| H A D | gfx_v10_0.c | 6086 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); in gfx_v10_0_cp_gfx_enable()
6093 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()
6095 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 197 #define mmCP_ME_CNTL … macro
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| H A D | gc_9_1_offset.h | 197 #define mmCP_ME_CNTL … macro
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| H A D | gc_9_2_1_offset.h | 191 #define mmCP_ME_CNTL … macro
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| H A D | gc_10_1_0_offset.h | 2199 #define mmCP_ME_CNTL … macro
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