Searched refs:mmCP_MEM_SLP_CNTL (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mxgpu_vi.c | 93 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
224 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
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| H A D | gfx_v6_0.c | 2664 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2667 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
2688 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2691 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
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| H A D | gfx_v9_0.c | 4995 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4998 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
5024 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
5027 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
5332 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); in gfx_v9_0_get_clockgating_state()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 255 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| H A D | gfx_7_2_d.h | 257 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| H A D | gfx_8_1_d.h | 289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| H A D | gfx_8_0_d.h | 289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2482 #define mmCP_MEM_SLP_CNTL … macro
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| H A D | gc_9_1_offset.h | 2759 #define mmCP_MEM_SLP_CNTL … macro
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| H A D | gc_9_2_1_offset.h | 2697 #define mmCP_MEM_SLP_CNTL … macro
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| H A D | gc_10_1_0_offset.h | 4821 #define mmCP_MEM_SLP_CNTL … macro
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